The present invention relates generally to an apparatus for testing a semiconductor memory device and, more particularly, to a semiconductor memory testing apparatus for relieving a memory cell of a defective memory under test from a defect taking a defect in a redundant circuit into consideration.
FIG. 8 is a block diagram showing a construction of a prior art semiconductor memory testing apparatus.
Referring to FIG. 6, the semiconductor memory testing apparatus is constructed of a central control unit 61 for controlling an operation of the whole apparatus, a pattern generator 62 for generating patterns of a variety of signals, a waveform shaping unit 66 for shaping waveforms in accordance with the patterns of the variety of signals which are received from the pattern generator 62 and inputting the variety of signals to a memory 68 under test, a judging unit 69 for judging whether the memory 68 under test is good or defective by comparing an output data signal from the memory 68 under test with an expected value pattern given from the pattern generator 62, and a defect analyzing memory unit 60 for receiving and storing a judgement signal given from the judging unit 69. The memory 68 under test is a semiconductor memory device as a subject to be tested.
The pattern generator 62 includes an address generator 63 for generating an address pattern, a data generator 64 for generating an input data pattern and an expected value pattern, and a control signal generator 65 fox generating a control signal pattern. The waveform shaping unit 66 includes a pattern selecting unit 67 for selecting any one of the patterns of the variety of signals. The defect analyzing memory unit 60 includes an address setting unit 71 for converting an address pattern an address to be tested within the memory 68 under test into an address when the defect analyzing memory 72 is stored with the judgement signal in accordance with a structure of the memory 68 under test, and the defect analyzing memory 72 for storing the judgement signal transmitted from the judging unit 69.
Based on a test program, the central control unit 61 controls the pattern generator 62, the waveform shaping unit 66, the judging unit 69 and the defect analyzing memory unit 60 in accordance with the operation control signal via a bus line. The central control unit 61 also processes defect data (good "0", and defect: "1") in the defect analyzing memory unit 60, and writes data of "0"/"1" to the defect analyzing memory unit 60.
The address generator 63 of the pattern generator 62 generates an address pattern with respect to the memory 68 under test, and an address pattern with respect to the defect analyzing memory unit 60. The data generator 64 of the pattern generator 62 generates an input data pattern with respect to the memory 68 under test, and an expected value pattern with which the output data signal from the memory 68 under test is compared and contrasted. The control signal generator 65 of the pattern generator 62 generates a control signal pattern with respect to the memory 68 under test.
The waveform shaping unit 66 shapes the waveform in accordance with the patterns of the address signal, the input data signal and the control signal which are received from the pattern generator 62, and generates the input signals, i.e., the address signal, the input data signal and the control signal to the memory 68 under test. The pattern selecting unit 67 of the waveform shaping unit 66 is capable of selecting any one of the plurality of patterns serving as a basis of the input signals to the memory 68 under test.
The judging unit 69 compares the output data signal from the memory 68 under test with the expected value pattern from the pattern generator 62, thus judging whether the memory 68 under test is defective or not.
The address setting unit 71 of the defect analyzing memory unit 60 converts into an address when the defect analyzing memory 72 is stored with the judgement signal, an address pattern (an address pattern from the pattern generator 62) of an address of a memory cell area that is a test subject in the memory 68 under test, in accordance with the structure of the memory 68 under test. The defect analyzing memory 72 of the defect analyzing memory unit 60 is a memory, accessed with the address converted by the address setting unit 71, an address of which is written with the judgement signal indicating whether it is good or defective (good: "0", and defect: "1").
The semiconductor memory testing apparatus shown in FIG. 6 operates as follows.
In accordance with the operation control signals given from the central control unit 61, the pattern generator 62 makes the address generator 63, the data generator 64 and the control signal generator 65 generate the address pattern, the input data pattern and the expected value pattern, and the control signal pattern. The waveform shaping unit 66, upon receiving the address pattern, the input data pattern and the control signal pattern, selects each patterns among these patterns which corresponds to any one of the memory cell areas of the memory 68 under test, then shapes the waveform and input those in the form of an address signal, an input data signal and a control signal to the memory 68 under test. The memory 68 under test executes predetermined operations corresponding to those signals and outputs the output data signals. The judging unit 69 compares the output data signal from the memory 68 under test with the expected value pattern given from the pattern generator 62, then judges whether the memory 68 under test is well-conditioned or defective, and outputs a result thereof as a judgement signal. The judgement signal is supplied to the defect analyzing memory unit 60, at which time the address pattern supplied to the defect analyzing memory unit 60 from the pattern generator 62 is converted into the address of the defect analyzing memory 72 in accordance with the structure of the memory 68 under test, and the judgement signal is stored in this address of the defect analyzing memory 72.
There arise, however, the following problems inherent in the prior art semiconductor memory testing apparatus in the case of segmenting the defect analyzing memory into a plurality of regions, then storing these regions with a plurality of items of defect information on the memory under test and relieving the memory under test from the defect. Note that the defect analyzing memory is, it is herein assumed, segmented into the four regions and the defect information is stored in memory cell areas (A), (B), (C) and (D).
FIG. 9 is an explanatory diagram two-dimensionally illustrating how address spaces of the defect analyzing memory are allocated when storing the defect analyzing memory of the conventional semiconductor memory testing apparatus with the defect information. FIG. 10 is an explanatory diagram one-dimensionally illustrating how the address spaces of the defect analyzing memory are allocated when storing the defect analyzing memory of the conventional semiconductor memory testing apparatus with the defect information. All the regions of the defect analyzing memory are equally segmented into the four regions. These four regions are respectively formed with a memory cell defect (A) storage area 81, a memory defect (B) storage area 82, a memory defect (C) storage area 83 and a memory defect (D) storage area 84 stored with the defect information about the defective memory cells in the memory cell areas (A), (B), (C) and (D) in the memory under test.
A switching signal for controlling which regions to be accessed among the four equally-segmented regions of the defect analyzing memory, is a part of, e.g., the address signal, and hence it follows that any one of the four regions is selected by this signal. This signal for selecting any one of the four regions is most significant 2 bits o f, e.g., the address signal, and therefore the respective memory cell defect (A), (B), (C), (D) storage areas are formed in the four regions into which the whole defect analyzing memory is equally segmented by "4".
At this time, however, if there are not equalized capacities of the memory cell defect (A) storage area 81, the memory cell defect (B) storage area 82, the memory cell defect (C) storage area 83 and the memory cell defect (D) storage area 84 formed in the four regions into which the defect analyzing memory is segmented, the defect information is actually stored in only areas defined by the solid lines in FIGS. 9 and 10, which leads to a problem of causing a futility in the capacity of the defect analyzing memory.
For example, in the case that defect information of ordinary memory cells is stored in memory call defect (A) storage area 81, defect information of a row redundancy circuit is stored in memory cell defect (B) storage area 82, defect information of a column redundancy circuit is stored in memory cell defect (C) storage area 83 and defect information in a crossing part of the row and column redundancy circuits is stored in memory cell defect (D) storage area 84, when necessary storage capacity for the memory cell defect (A) storage area is assumed as 1, necessary storage capacities for the memory cell defect (B) and (C) storage areas 82 and 83 will usually be around 0.1 and the necessary storage capacity for the memory cell defect (D) will usually be around 0.01.
However, the address of each of the four segmented regions of the defect analyzing memory is structured of binary numbers, and it is required that the address space be increased double each time the address space is enlarged. Further, the address space needed for each region must be ensured corresponding to the address necessary for the region formed with the memory cell defect (A) storage area 81 having the largest capacity, and is therefore required as defined by the axis of abscissa and the axis of ordinates shown in FIG. 7. Accordingly, the regions formed with the memory cell defect (A) storage area 81, the memory cell defect (B) storage area (2, the memory cell defect (C) storage area 83 and the memory cell defect (D) storage area 84, are ensured in accordance with the address needed for the region formed with the memory cell defect (A) storage area 81 as described above. Therefore. as shown in FIG. 9, the area to be used in fact is only the area defined by the solid line, and the area defined by a dotted line drawn outwardly is an unused area. To express it one-dimensionally, as shown in FIG. 10, gap areas 80 unused for storing the defect information are formed, and is it can be recognized that there must be the futility in terms of the capacity of the defect analyzing memory.
Furthermore, the switching signal for controlling which region to be accessed among the four equally segmented regions of the defect analyzing memory be, it is required, generated as a part of the address signal. This switching signal has, however, no direct connection with a register calculation performed by the pattern generator in order to actually have an access to the memory cell of the memory under test. Therefore, even when trying to continuously test between the respective memory cells of the memory under test, the pattern generate needs to reset the address pattern during the test for each memory cell, resulting in such a problem that the continuous test is unable to be performed.